Guide to computer processor architecture / Bernard Goossens

Public ISBD Titre : Guide to computer processor architecture : A RISC-V approach, with high-level synthesis Type de document : texte imprimé Auteurs : Bernard Goossens, Auteur Editeur : Newyork;Paris;Milan;Berlin;Londres;Amsterdam [Usa;France;Italie;Allemagne;Engleterre;Hollande] : Springer Année de publication : 2023 Collection : Undergraduate topics in computer science Importance : 438 p. Format : 24 cm. ISBN/ISSN/EAN : 978-3-031-18022-4 Note générale : Réf. bibliographiques. Index 431 Langues : Anglais Mots-clés : Computer architecture  RISC (microprocessors)  Floating-point instructions Résumé : This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002. Guide to computer processor architecture : A RISC-V approach, with high-level synthesis [texte imprimé] / Bernard Goossens, Auteur . - Newyork;Paris;Milan;Berlin;Londres;Amsterdam (Usa;France;Italie;Allemagne;Engleterre;Hollande) : Springer, 2023 . - 438 p. ; 24 cm.. - (Undergraduate topics in computer science) . ISBN : 978-3-031-18022-4 Réf. bibliographiques. Index 431 Langues : Anglais Mots-clés : Computer architecture  RISC (microprocessors)  Floating-point instructions Résumé : This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.

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Introduction to compiler design / Torben Ægidius Mogensen

Public ISBD Titre : Introduction to compiler design Type de document : texte imprimé Auteurs : Torben Ægidius Mogensen, Auteur Mention d'édition : Third edition Editeur : Newyork;Paris;Milan;Berlin;Londres;Amsterdam [Usa;France;Italie;Allemagne;Engleterre;Hollande] : Springer Année de publication : 2024 Collection : Undergraduate topics in computer science Importance : 287 p. Format : 24 cm. ISBN/ISSN/EAN : 978-3-031-46459-1 Note générale : Includes bibliographical references and index Langues : Anglais Mots-clés : Compiler  Compilateurs (logiciels) Résumé : The third edition of this textbook has been fully revised and adds material about the SSA form, polymorphism, garbage collection, and pattern matching. It presents techniques for making realistic compilers for simple to intermediate-complexity programming languages. The techniques presented in the book are close to those used in professional compilers, albeit in places slightly simplified for presentation purposes. "Further reading" sections point to material about the full versions of the techniques. All phases required for translating a high-level language to symbolic machine language are covered, and some techniques for optimising code are presented. Type checking and interpretation are also included. Aiming to be neutral with respect to implementation languages, algorithms are mostly presented in pseudo code rather than in any specific language, but suggestions are in many places given for how these can be realised in different language paradigms. Depending on how much of the material from the book is used, it is suitable for both undergraduate and graduate courses for introducing compiler design and implementation. Introduction to compiler design [texte imprimé] / Torben Ægidius Mogensen, Auteur  . -  Third edition . - Newyork;Paris;Milan;Berlin;Londres;Amsterdam (Usa;France;Italie;Allemagne;Engleterre;Hollande) : Springer, 2024 . - 287 p. ; 24 cm.. - (Undergraduate topics in computer science) . ISBN : 978-3-031-46459-1 Includes bibliographical references and index Langues : Anglais Mots-clés : Compiler  Compilateurs (logiciels) Résumé : The third edition of this textbook has been fully revised and adds material about the SSA form, polymorphism, garbage collection, and pattern matching. It presents techniques for making realistic compilers for simple to intermediate-complexity programming languages. The techniques presented in the book are close to those used in professional compilers, albeit in places slightly simplified for presentation purposes. "Further reading" sections point to material about the full versions of the techniques. All phases required for translating a high-level language to symbolic machine language are covered, and some techniques for optimising code are presented. Type checking and interpretation are also included. Aiming to be neutral with respect to implementation languages, algorithms are mostly presented in pseudo code rather than in any specific language, but suggestions are in many places given for how these can be realised in different language paradigms. Depending on how much of the material from the book is used, it is suitable for both undergraduate and graduate courses for introducing compiler design and implementation.

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